INPs are used in computer network systems for providing HBA, router, and switch capabilities for particular protocol networks connected to a host through a host interface. An example of an INP 110 is shown in FIG. 1, which may be formed on a single silicon integrated circuit die packaged inside a ceramic, metal, or plastic housing to form a unitary component. INP 110 includes a shared memory crossbar module 112 which is controlled by a flow identification/scheduler module 114 through a bus 128. The flow identification/scheduler module 114 operates under the control of the Application Processor (APEX) module 116 acting through the bus 130, and maps the passages of crossbar locations inside the shared memory crossbar module 112. The APEX 116 in the example of FIG. 1 contains ten core processors for executing firmware, denoted as processors 118-127.
The shared memory crossbar module 112 is connected to Protocol Coordination Stage (PCS) modules 132 and 134 through buses 136 and 138, respectively. PCS module 132 is connected to and controls the operation of Media Access Controller (MAC) modules 140, 142, 144, and 146. The MAC modules 140, 142, 144, and 146 are identical hardware interfaces capable of each communicating using the FC protocol at 1 Gigabits per second (Gbps) or 2 Gbps speeds. The speed and protocol settings for the for the MAC modules 140, 142, 144, and 146 are controlled by the PCS 132, which operates in response to control signals from a bus (not shown) connecting the PCS 132 to the APEX 116. A parallel 10 Gbit (X Gbit) Medium-Independent Interface (XGMII) port 147 may be provided from the PCS 132, as determined by control signals originating from the APEX 116. The 10 Gb XGMII interface is not coupled to any of the four MAC modules.
In the example of FIG. 1, PCS 134 is connected to MAC modules 148, 150, 152, and 154 in the same way that PCS 132 is connected to MAC modules 140, 142, 144, and 146. The construction of PCS 134 is the same as the construction of PCS 132, but PCS 134 operates independently of the PCS 132. MAC modules 148, 150, 152, and 154 have the same construction as the MAC modules 140, 142, 144, and 146.
A System Packet Interface level 4, phase 2 (SPI4.2) interface module 156 is connected to the shared memory crossbar module 112 through bus 158. The SPI4.2 interface module 156 may be connected to high-speed I/O through external bridges, or to a backplane through a switch-chip fabric, or to other network processors (not shown). Another SPI4.2 interface module 160 is connected to the shared memory crossbar module 112 through bus 162. The SPI4.2 interface module 160 may also be connected to high-speed Input/Output (I/O) through external bridges, or to a backplane through a switch-chip fabric, or to other network processors (not shown).
Each of the MACs 140, 142, 144 and 146 may be coupled to a separate, off-chip SERializer/DESerializer modules (SERDES). The function of the off-chip SERDES is to provide electronic signals in the FC protocol to off-chip transceivers (not shown), which may be optical transceivers for connection to fiber optic cables or electrical transceivers for connection to electrical cables. The MACs 148, 150, 152 and 154 may also be coupled to separate, off-chip SERDES (not shown).
A Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) controller 164 is connected to the scheduler 114 through bus 166. The function of the controller 164 is to control the sending and receiving of data to and from an external DDR memory module (not shown) connected to an external bus 168 of the controller.
A support processor 115 handles certain processing tasks not otherwise covered by the APEX 116, and has an external connection 117. A Joint Test Action Group (JTAG) module 168 has an external connection 170, and is used for boundary scan testing of the hardware contained within INP 110. Serial flash memory 172 has an external connection 174, and is a non-volatile reprogrammable memory which may be loaded through the connection to store firmware for operation of APEX 116 and support processor 115.
FIG. 2 is an illustration of firmware and software structures 210 for use with the INP of FIG. 1 (shown as an INP hardware block in FIG. 2). The structures 210 serve to provide the computer codes for activating the INP hardware block, and for interacting with a host Operating System (OS) software structure (not shown) such as Linux or Microsoft Windows. On-chip firmware 214 may be downloaded into the INP, and are for execution by the APEX module and support processor of FIG. 1. The firmware 214 interacts with the hardware through connection 218.
A Platform Integration Module (PIM) 222 is firmware code for execution by the support processor of FIG. 1, and includes a boot startup and Power On Self Test (POST) module 224, online and offline diagnostic program module 226, configuration and device management module 228, and status and debug log module 230. The PIM 222 may be accessed through the connection 232. The connection 232 is preferably the same as the connection 117 of FIG. 1. This module can be customized for each platform that the INP is integrated with.
The on-chip firmware 214 and PIM 222 may be accessed by an external software operating system through a hardware abstraction layer 234, or may be directly accessed through a connection 236. The layer 234 is a part of a software driver program which also includes an infrastructure services module 238 and a virtualization and basic copy services module 240. The software driver including the layer 234 and modules 238 and 240 is to be executed as a program on an external host computer processor (not shown) under the control of a host operating system software structure (not shown).
The infrastructure services module 238 includes a discovery and initiator driver 248, a statistics driver 250, a FC initiator and target driver 252, and a device management driver 254. The virtualization and basic copy services module 240 includes a virtualization services driver 258 and a basic copy services driver 260.
The PCIe specification entitled “PCI Express™ Base Specification Revision 1.1 Mar. 28, 2005,” incorporated by reference herein, available from the web site www.pcisig.org, defines the terms “configuration,” “device,” “EndPoint” (EP), “function”, “lane,” “link,” and “Root Complex” (RC) as used in connection with PCIe bus designs. Each PCIe device connected to the PCIe bus is given a configuration. A problem with the PCIe standard is that it does not describe a way for a HBA to present multiple PCIe device configurations simultaneously, and to change the PCIe device configurations. In addition, the PCIe standard does not describe a way for a HBA to present emulated PCIe device configurations through the PCIe bus to a host computer using memory apertures in the host memory.
Another industry specification, the Advanced Switching Interconnect Sig (ASI SIG™) specification entitled “Advanced Switching Core Architecture Specification Revision 1.1—Final, November 2004”, incorporated herein by reference, is available from the web site www.asi-sig.org, is based on the PCIe architecture, and adds transaction layer capabilities to enable flexible protocol encapsulation, peer-to-peer transfers, dynamic reconfigurations, and multicast. The ASI SIG™ specification describes the use of “apertures” for device configuration. The basic purpose of ASI SIG™ is to create a switching fabric using PCIe links. However, the ASI SIG™ specification does not provide a way for configurations to be changed in an aperture by a HBA, or for device configurations to be emulated in firmware by a HBA.